The StrongARM is a family of microprocessors that implemented the ARM V4 instruction set architecture (ISA). It was developed by Digital Equipment Corporation (DEC), and later sold to Intel who continued to manufacture it, before replacing it with the XScale.
[edit] History
The StrongARM was a collaborative project between DEC and ARM to create a faster microprocessor based on (but not totally compatible with) the existing ARM line. The StrongARM was designed to address the upper-end of the low-power embedded market, where users needed more performance than the ARM could deliver while being able to accept more external support. Targets were devices such as newer personal digital assistants and set-top boxes.[1]
The project was set up in 1995, and quickly delivered their first design, the SA-110.
This was immediately incorporated into newer versions of the Apple Newton, the Acorn Risc PC, Eidos Optima video editing system, as well as a number of other products.
StrongARM was sold to Intel as part of a lawsuit settlement in 1997.[2] Intel used the StrongARM to replace their ailing line of RISC processors, the i860 and i960.
The StrongARM SA-1110 was used in the Simputer.
StrongARM was later discontinued, replaced by the Intel XScale.
[edit] Description
The StrongARM family are faster versions of the existing ARM processors with a somewhat different instruction set. Clocked at 206MHz they can perform up to 235 MIPS (1.14 MIPS/MHz). They have limited software compatibility with the earlier ARM families due to their separate caches for data and instructions, which causes self-modifying code to fail. These features were later included in some ARMv4 architectures (notably, the ARM/Texas Instruments ARM925). The StrongARM has an "invalidate cache line" instruction to let the CPU know to reload from main memory. This situation arises rarely in typical software however, and StrongARM is certainly not the only processor to have made such a sacrifice. The Motorola 68020, for instance, caused similar compatibility problems for any software designed for the earlier 68000 and 68010 models.
The StrongARM is designed with slow (and therefore low cost) memory in mind. The StrongARM has a 32-way set associative cache which works on virtual addresses. The high set associativity allows a higher hit rate than competing designs, and the use of virtual addresses allows memory to be simultaneously cached and uncached. A write buffer allows writes to main memory to happen without the CPU stalling, increasing the efficiency of the design.
Derivatives included the SA-1100 (initially targeted for PDAs) and SA-1500 (initially targeted for set top boxes)[3][4]. The latter processor was designed and manufactured in low volumes by DEC but was never put into production by Intel.
[edit] References
- ^ Montanaro, James et al. "A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor". Digital Technical Journal, Volume 9, Number 1, 1997. pp. 49–62
- ^ Erich Luening (1997-10-27). "Intel, Digital settle suit". CNet news.com. http://news.cnet.com/2100-1023-204668.html. Retrieved on 2008-07-29.
- ^ "Intel to reveal details on StrongARM chip". EETimes. http://www.eetimes.com/news/98/1018news/strongarm.html. Retrieved on 2008-12-03.
- ^ "SA-1500: A 300MHz RISC CPU with Attached Media Processor". http://www.hotchips.org/archives/hc10/3_Tue/HC10.S8/HC10.8.3.pdf. Retrieved on 2008-12-03.
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